1. Field of the Invention
The present invention relates to an access control method for a memory, a memory controller for controlling access to the memory, and a data processing apparatus. More specifically, the present invention relates to a technology capable of selecting a valid storage area in an optimum manner within a memory where a plurality of storage areas are provided.
2. Description of the Related Art
In some cases, it is desirable that data writing and data reading to/from a memory can be simultaneously executed. One of those typical examples is a flash memory into which computer programs executed by central processing unit (CPU) have been written. When a flash memory is used in which data writing and data reading cannot be executed at the same time, an instruction code cannot be read from the flash memory during the data writing operation, so processing by a CPU is interrupted. In the above a flash memory, it is desirable that an instruction code of a program can be read even while the data writing operation is carried out.
One measure for simultaneously performing data writing and data reading is to constitute a memory by a plurality of memory blocks which can be independently accessed. FIG. 1 is a block diagram for showing a structure of a conventional memory 100 arranged in the above-mentioned manner. The memory 100 is equipped with two memory blocks, namely, a memory block 0 and a memory block 1. While data is read from the memory block 0, data can be written in the memory block 1.
When the above measure is applied to a flash memory, a problem arises. That is, in a flash memory, a write parameter and security setting data are required to be stored in a memory array. A write parameter is data which is used in data writing. For instance, data indicative of a structure of a sector is contained in the write parameter. Security setting data is data which is employed to set security of a flash memory. The security setting data indicates whether writing and erasing of an entire storage area of the flash memory and/or each of memory blocks thereof are permitted or prohibited. Based upon the security setting data, writing/erasing of the entire storage area of the flash memory can be prohibited, and writing/erasing of the respective memory blocks thereof can be prohibited. In order to change setting of security, security setting data needs to be updated.
The problem occurs in a case where security setting data is updated. It is desirable that updating of security setting data be carried out in association with a writing operation. However, in a structure that a write parameter and security setting data are stored in a specific single memory block, while a writing operation for another memory block is carried out, the write parameter and the security setting data cannot be updated.
FIG. 2A is an explanatory diagram for describing the above-mentioned problem. A semiconductor device 200 of FIG. 2A is equipped with a flash memory 201 and a memory controller 202. The flash memory 201 is provided with two memory blocks, namely, a memory block 0 and a memory block 1, and each of the memory blocks is equipped with a user data area and an expansion area. A write parameter and security setting data are stored in an expansion area 0 of the memory block 0. An expansion area 1 of the memory block 1 is an unused area. In the case where a reading operation from the memory block 0 and a writing operation in the memory block 1 are carried out at the same time, first, the memory block 1 is set to a write mode and the memory block 0 is set to a read mode. Subsequently, a write parameter is read from the expansion area 0, and the memory controller 202 writes data in the memory block 1 by using the read write parameter. In the above-mentioned operations, rewriting of the security setting data cannot be continuously carried out after the data writing to the memory block 1. In order to rewrite the security setting data, the memory block 0 is required to be changed from the read mode to the write mode. However, rewriting of the security setting data in the above-mentioned manner is not preferable, because the process of the writing operations becomes cumbersome.
As one of measures capable of solving the above-mentioned problem, a write parameter and security setting data are stored in each of memory blocks of a flash memory. FIG. 2B is a block diagram for indicating a structure of the above-mentioned flash memory. In a semiconductor device 200 of FIG. 2B, an expansion area 0 and an expansion area 1 are prepared for a memory block 0 and an memory block 1, respectively, and write parameters and security setting data are stored in each of the expansion areas 0 and 1.
In the semiconductor device 200 of FIG. 2B, for example, a reading operation from the memory block 0 and a writing operation in the memory block 1 are carried out in the following manner. First, after the write parameter and the security setting data have been read, the memory block 0 is set to a read mode, whereas the memory block 1 is set to a write mode. Data is written in the memory block 1 by employing the read write parameter. Subsequently, the security setting data of the expansion area 1 of the memory block 1 is updated. The memory block 1 is maintained under a condition that the memory block 1 has been set to the write mode until updating of the security setting data of the expansion area 1 is finished. The security setting data of the expansion area 0 is not updated.
In the above-mentioned operations, because updating of the security setting data is performed only in any one of those two expansion areas 0 and 1, it is necessary to judge in which of the expansion areas 0 and 1 the valid security setting data (i.e., latest data) is stored. As the most typical method of identifying in which of a plurality of areas the valid data is stored, flags are employed, as disclosed in, for example, JP 10-50087 A. For instance, as shown in FIG. 3, a flag 0 and a flag 1 are prepared for a data area 0 and a data area 1, respectively, in order to indicate in which of those data areas 0 and 1 the valid data is stored. When the data stored in the data area 0 is valid, the flag 0 is set to “1”, and the flag 1 is reset to “0”. On the other hand, when the data stored in the data area 1 is valid, the flag 1 is reset to “1”, and the flag 0 is reset to “0”.
Further, JP 2005-38518 A discloses that a 2-bit memory selector is prepared for each of management areas of the two memories in order to indicate which of those two memories is valid. In the technology disclosed in the above-mentioned JP 2005-38518 A, a memory from which data should be read is judged from both the data of the memory selectors of the two memories. In this conventional technique, rewriting of the memory selectors is carried out by setting one memory of the two memories to a program mode and another memory to an erase mode.
The present inventor has recognized that the technology for indicating the valid area by setting the flag to 1, as disclosed in JP 10-50087 A, has the following problem. That is, if both the flags 0 and 1 become “1” due to a certain failure, then the valid data area becomes indefinite. The condition in which the valid data area becomes indefinite is not preferable from a viewpoint of securing operational stabilities of the semiconductor device.
In addition, the technology for indicating the valid area by setting the flag to 1, as disclosed in JP 10-50087A, has another problem. That is, in order to change the valid areas, the flags for all of the areas must be rewritten. For instance, in order to change such a status that a flag 0 of a memory 0 has been set to “1” into another status that a flag 1 of a memory 1 has been set to “1”, the flag 1 of the memory 1 must be set to “1” and also the flag 0 of the memory 0 must be reset to “0”. However, such a sequential operation is not suitable in the case where a writing operation is performed with respect to one of the memories 0 and 1, and a reading operation is performed with respect to another memory.
For instance, the following case can be considered: the writing operation for the memory 1 and the reading operation for the memory 0 are carried out at the same time. In this case, in order that the flag 0 of the memory 0 is reset to “0”, the operation mode of this memory 0 must be changed from the read mode to the write mode. The flag rewriting operation in the above-mentioned manner is not preferable, because the operation sequence become cumbersome.
Also, the present inventor considers that the technology disclosed in JP 2005-38518 A cannot solve the above-mentioned problems.